(Monday 8th July)
Killer-mobiles: the way towards energy efficient High Performance Computers?
Mateo Valero, BSC - Microsoft Research Centre
It is widely recognized that Exascale systems will be constrained by power. The Mont-Blanc project aims to build an alternative approach towards Exascale based on aggregating parts from the embedded and mobile market, which offer a better FLOPS/Watt ratio and a lower unit cost, at the expense of lower peak performance per chip. HPC systems built from these parts will require a higher number of processors, or resort to extensive use of compute accelerators. Using a higher number of chips increases the available memory bandwidth, alleviating the bandwidth wall, but increases the pressure on the interconnection network.
The use of a high number of processors and accelerators, and the increased pressure on the interconnect require extensive code optimizations to achieve strong scaling, point to point synchronizations, and overlap data transfer with computation. The role of the OmpSs parallel programming model is paramount, as the key enabling technology that hides the complexity from the programmer, and transparently performs all the required optimizations.
In this talk, we will review the design philosophies of several vendors, including HPC compute accelerators, and ARM-based mobile application processors in terms of peak performance, memory bandwidth, and energy efficiency; and we will review how the OmpSs programming models exploits the benefits of the Mont-Blanc approach while overcoming the drawbacks.
About Mateo Valero
Mateo Valero is a professor in the Computer Architecture Department at UPC, in Barcelona. His research interests focuses on high performance architectures. He has published approximately 600 papers, has served in the organization of more than 300 International Conferences and he has given more than 400 invited talks. He is the director of the Barcelona Supercomputing Centre, the National Centre of Supercomputing in Spain. Dr. Valero has been honoured with several awards. Among them, the Eckert-Mauchly Award, Harry Goode Award , the “King Jaime I” in research and two National Awards on Informatics and on Engineering. He has been named Honorary Doctor by the University of Chalmers, by the University of Belgrade, by the Universities of Las Palmas de Gran Canaria and Zaragoza in Spain and by the University of Veracruz in Mexico. "Hall of the Fame" member of the IST European Program (selected as one of the 25 most influents European researchers in IT during the period 1983-2008. Lyon, November 2008) In December 1994, Professor Valero became a founding member of the Royal Spanish Academy of Engineering. In 2005 he was elected Correspondant Academic of the Spanish Royal Academy of Science, in 2006 member of the Royal Spanish Academy of Doctors, in 2008 member of the Academia Europaea and in 2012 Correspondant Academic of the Mexican Academy of Sciences. He is a Fellow of the IEEE, Fellow of the ACM and an Intel Distinguished Research Fellow.
(Tuesday 9th July)
SyNAPSE: Scalable Energy-Efficient Neurosynaptic Computing
Jun Sawada, IBM Austin Research Laboratory
SyNAPSE (Systems of Neuromorphic Adaptive Plastic Scalable Electronics) is a project aiming to build a brain-like computing system in the scale of mammalian brains. IBM, with collaborators from multiple US universities, combines the principles of nanoscience, neuroscience and supercomputing to simulate and emulate the brains abilities for sensation, perception, action, interaction and cognition while rivaling its low power consumption and compact size.
One key component of creating a scalable neuromorphic computing is energy efficiency. In the phase one of this project, IBM demonstrated an ASIC neuromorphic chip using asynchronous circuits. This chip achieved an extremely low-power computation of 45pJ per spike. We envision much larger neuromorphic computing systems based on this concept design.
About Jun Sawada
Jun Sawada graduated Kyoto University in Japan with BS and MS degrees in Mathematics. He received his Ph.D in Computer Sciences from the University of Texas at Austin for the study in formal verification of hardware, VLSI microarchitecture, theorem proving and automated deduction. In 2000, he joined IBM Austin Research Laboratory, and he is an IBM research staff member since then. At IBM, he has been involved in many chip development projects including the BlueGene/Q project. Recently he is working on the SyNAPSE project, leading the neuromorphic hardware design team.
(Wednesday 10th July)
Towards a Distributed Search Engine
Ricardo Baeza-Yates, Yahoo! Research
In the ocean of Web data, Web search engines are the primary way to access content. As the data is on the order of petabytes, current search engines are very large centralized systems based on replicated clusters. Web data, however, is always evolving. The number of Web sites continues to grow rapidly (more than 200 million) and there are easily more than 100 billion indexed pages. On the other hand, Internet users are above one billion and hundreds of million of queries are issued each day. In the near future, centralized systems are likely to become less effective against such a data-query load, thus suggesting the need of fully distributed search engines. Such engines need to maintain high quality answers, fast response time, high query throughput, high availability and scalability; in spite of network latency and scattered data. In this talk we present the main challenges behind the design of a distributed Web retrieval system and our research in all the components of a search engine: crawling, indexing, and query processing.
About Ricardo Baeza-Yates
Ricardo Baeza-Yates is VP of Yahoo! Labs for Europe and Latin America, leading the labs at Barcelona, Spain and Santiago, Chile, as well as supervising a team in San Francisco. Until 2005 he was the director of the Center for Web Research at the Department of Computer Science of the Engineering School of the University of Chile; and ICREA Professor at the Department of Technology of the University Pompeu Fabra in Barcelona, Spain. He is co-author of the best-seller book Modern Information Retrieval, published in 1999 by Addison-Wesley with a second edition in 2011, as well as co-author of the 2nd edition of the Handbook of Algorithms and Data Structures, Addison-Wesley, 1991; and co-editor of Information Retrieval: Algorithms and Data Structures, Prentice-Hall, 1992, among more than 200 other publications. He has received the Organization of American States award for young researchers in exact sciences (1993) and several national awards in Chile. In 2003 he was the first computer scientist to be elected to the Chilean Academy of Sciences. During 2007 he was awarded the Graham Medal for innovation in computing, given by the University of Waterloo to distinguished ex-alumni. In 2009 he was awarded the Latin American distinction for contributions to CS in the region and became an ACM Fellow, followed in 2011 by an IEEE Fellowship.